Source: Semiconductor Industry Watch (ID: icbank) compiled from semi wiki, thanks.
Packaging used to be an afterthought in semiconductor manufacturing. You make a little chip, and then you connect it, and you go on your happy way. But as Moore's Law stretched, engineers realized they could use all parts of a chip, including packaging, to make the best products. Improved packaging gives you significant benefits because there are thicker sheets of metal for better conductivity, and the I/O (input/output) problem is still one of the biggest problems facing semiconductors.
More surprisingly, no packaging company has ever been considered as important as the traditional front-end manufacturing process. The encapsulated supply chain is often considered the "back end" and is viewed as a cost center, similar to the front and back office of a bank. But now as the front end tries to extend its boundaries, a whole new area of focus has emerged, and that is the emphasis on encapsulation. We will discuss various processes so that you are no longer confused as you study this part of semiconductor packaging and understand what 2.5D or 3D packaging means.
Looking back at the development of packaging over the past few decades, its simplified evolution is DIP> QFP > BGA > POP/SiP > WLP.
Obviously there are many different encapsulation techniques, but we'll discuss simplification techniques that broadly represent each type and then slowly bring them up to the present. I also really like the following high-level overview (which is outdated but still true).
In the initial stages of encapsulation, items are usually housed in ceramic or metal canisters and sealed (air-tight) for the greatest possible reliability. This applies primarily to aerospace and military functions that require the highest reliability. However, this was not feasible for most of our daily use cases, so we started using plastic packaging and dual in-line packaging (DIP).
DIP package (1964-1980s)
DIP was introduced in the 1970s and dominated the decade before surface mount technology was introduced. The DIP uses a plastic casing around the actual semiconductor and features two parallel rows of protruding electrical pins, called lead frames, connected to the PCB (printed circuit board) below.
The actual die is then connected via bonding wires to two lead frames that can be connected to a printed circuit board (PCB).
Like many early semiconductor inventions, DIP was created by Fairchild semi in 1964. The DIP package is a retro iconic design, and the design choice is understandable. The actual bare sheet would be sealed entirely in resin, thus providing high reliability and low cost, and many of the earliest iconic semiconductors were packaged this way. Note that the die is wired to the external lead frame, making it a "lead bonding" encapsulation method. More on that later.
Here's the Intel 8008 -- actually one of the first modern microprocessors. Please note that it is the iconic DIP packaging. So if you see those funky photos of semiconductors that look like little spiders, that means it's just a DIP package semiconductor
Each of these small metal pieces is then welded to the PCB, where it makes contact with other electrical components and the rest of the system. Here is how to solder the package to the PCB board.
PPCBS themselves are usually made of copper or other electrical components laminated with non-conductive materials. The PCB can then route power from one place to another, allowing the components to connect and communicate with each other. Note the thin wires welded to the PCB between each circuit, these are embedded wires that are used as conduits from piece to piece. That is the "package" part of the package, and the PCB is the highest level of the package.
While there were other versions of DIP, it was actually time to move to the next packaging technology paradigm that began in the 1980s, namely surface mount packaging.
Surface mount package
(1980s to 1990s)
Instead of installing products through DIP, the industry has introduced surface mount technology (SMT). As implied, the package is mounted directly onto the PCB's surface and allows for more components to be used on one substrate and reduces costs. Below is a picture of a typical surface mount package.
There are many variations of this package and it was a workhorse for a long time during the heyday of semiconductor innovation. It should be noted that instead of two lead frames, all sides now have 4 surfaces installed on the PCB. This meets the general need for packaging to take up less space and increase connection bandwidth or I/O. Each additional advance keeps this in mind, and is a model worth watching.
The process used to be manual, but is now highly automated. In addition, this actually causes a lot of problems for PCBS, such as popcorn. Popcorn is when the moisture inside the plastic package is heated during the welding process and can cause problems with the PCB due to rapid reheating and cooling. Another thing to note is that complexity and failures increase with each increase in the encapsulation process.
Ball grid package and chip level package
(1990s to 2000s)
As the requirements for semiconductor speed continue to increase, so does the need for better packaging. While QFN and other surface mount technologies clearly continue to proliferate, I'd like to introduce you to the beginnings of package design that we'll have to understand in the future. This is the beginning of a ball or ball grid array (BGA) package in a broader sense.
These balls or bumps are called solder bumps/solder balls
This is what a ball grid array looks like, allowing a piece of silicon to be mounted directly onto the PCB or substrate from below, instead of just taping the corners of all 4 ends as with previous surface mount techniques.
So this is just another continuation of the trend I outlined above, taking up less space and more connections. Instead of delicately wiring the wrapper on each side, we now wire one wrapper directly to the other. This leads to higher density, better I/O (a synonym for performance), and now increased complexity in how to check that BGA encapsulation works. So far, the focus has been on visual inspection and testing of the package. Now we can't see the encapsulation, so there's no way to test it. X-rays are fed in for inspection and, eventually, more sophisticated techniques are used.
The solder joint is also something I want you to remember, it is now the main way to glue to each other, because it is the most common type of encapsulation interconnect mode.
Modern Package (2000-2010s)
We are now moving into the modern packaging era. Many of the encapsulation schemes described above are still in use today, but you will begin to see more and more encapsulation types that will become more relevant in the future. I'm going to start describing these now. To be fair, many of these upcoming technologies were invented in previous decades, but were not widely used until later due to cost.
Flip chip
This is one of the most common types of encapsulation you're likely to read or hear about. I'm glad I can define it for you, because there's never been a satisfactory explanation in the primer books I've read so far. Flip chips were an early invention of IBM and are often abbreviated to C4. In the case of flip chips, it is really not a stand-alone form of packaging, but a style of packaging. Almost whenever there is a solder bump on the chip. Instead of a lead bond for interconnection, the chip is flipped to face the other chip with a connecting substrate in between, thus a "flip chip".
I don't want you to just take it from that awkward sentence, but I want to give you an example from Wikipedia, which actually has some of the best introductions I've ever seen. Let us walk you through these steps.
1. The IC is created on the wafer
2. The pad is metallized on the surface of the chip
3. Solder spots are deposited on each pad
4. Cut the chip
5. The chip is turned over and positioned so that the ball faces the circuit
6. Then remelt the ball
7. The bottom of the installed chip is filled with electrical insulating adhesive
Lead bonding
Note how flip chips differ from lead bonding. Remember the DIP package at the top? That's lead bonding, where the chip uses a lead to bond to another metal and then solder to the PCB. Again, lead bonding is not a specific technology, but rather an older set of technologies containing many different types of encapsulation. I think it's best described as a flip chip. Wirebond is a pioneer in flip chips.
Honestly, if you make it this far -- you're a champion. I think that's really all you need to know. There is plenty of variation in each form factor, just think of these as the overarching themes that govern them.
Advanced Packaging (2010s to present)
We are slowly entering the era of "advanced packaging" semiconductors, and I want to talk now about some of the higher concepts. There are actually various levels of "encapsulation" suitable for this thought process. Most of the packaging we've talked about before has focused on chip packaging to PCBS, but the beginning of advanced packaging really started with mobile phones.
Mobile phones are in many ways a huge pioneer in many aspects of advanced packaging. That makes sense! Mobile phones, in particular, contain a lot of silicon in the smallest possible space and are much denser than laptops or computers. Everything has to be passively cooled, as thin as possible of course. Every year Apple and Samsung release a faster but thinner phone that pushes encapsulation to new limits. Many of the concepts I'll discuss started with smartphone packaging and have now moved to other parts of the semiconductor industry.
Chip level package (CSP)
Chip-level packaging is actually a bit broader than it sounds, and originally referred to as chip-level packaging. The technical definition is a package that is not more than 1.2 times the size of the bare sheet itself, and must be single bare sheet and attached. In fact, I've introduced you to the concept of CSP by flipping chips. But CSPS have really taken it to a new level with smartphones.
The 2010s have made CSPS the order of the day, and everything in this photo is 1.2 times the size of a chip chip and focused on saving as much space as possible. There are many different styles of the CSP era, and flip chips, right baseboards, and other technologies are part of this category. But I don't think knowing the details does you a lot of good.
Wafer Level Packaging (WLP)
But there is an even smaller level -- this is the "ultimate" chip-level package size, or wafer-level package. This is almost just putting the packaging on the actual silicon chip itself. The package is silicon chip. It's thinner, has the highest level of I/O, and is obviously very hot and difficult to make. The advanced packaging revolution is currently on the scale of CSPS, but the future is all about wafers.
This is an interesting evolution where encapsulation is contained by the actual silicon itself. A chip is a package, and vice versa. It's really expensive compared to just soldering some balls onto the chip, so why do we do it? Why the current obsession with advanced packaging?
The future of advanced packaging
This is the culmination of a trend I've been writing about for a long time. Heterogeneous computing is not only the story of specialization, but also the story of how we put all these specialized pieces together. Advanced packaging is a key driver in making all this work.
Let's look at M1 -- a classic heterogeneous computing configuration, specifically their uniform memory structure. For me, M1 is not a "wow" moment, but a unique moment before and after heterogeneous computing. M1 is showing what the future looks like, and many will soon follow Apple's lead. Note that the actual SOC (system-on-chip) is not heterogeneous, but rather a custom package that brings memory close to the SOC.
This may be an edited photo - but note that the PCB has no wires - this may be because of their excellent 2.5D integration.
Another very good example of advanced packaging is Nvidia's new A100. Notice again that there are no wires on the PCB.
See their white paper for an introduction.
Unlike traditional GDDR5 GPU board designs, which require a large number of discrete memory chips around the GPU, HBM2 consists of one or more vertical stacks of multiple memory bare chips. The memory die is connected using microscopic wires created through silicon holes and microbumps. An 8 Gb HBM2 nude contains more than 5,000 silicon through holes. The passive silicon intermediary layer is then used to connect the memory stack to the GPU chip. The combination of HBM2 stack, GPU chip, and silicon intermediary layer is packaged in a single 55mm x 55mm BGA package. See Figure 9 for an illustration of the GP100 and two HBM2 stacks, and Figure 10 for a micrograph of the actual P100 with GPU and memory.
The point here is that the best silicon in the world is being made one way, and the revolution hasn't stopped. Let's learn more about the words above and translate them into English. The first is more information on the overall categories of advanced packaging, 2.5D and 3D packaging.
2.5D package
The 2.5D is a bit like the accelerated version of the flip chip we mentioned above, but instead of stacking individual chips onto PCBS, the chips are stacked on top of a single intermediary layer. I think that's a pretty good picture.
2.5D is like having a basement door to your neighbor's house, and is actually a convex block or TSV (through a silicon through hole) that goes into the silicon intermediary layer below you and connects you to your neighbor. It's no faster than your actual on-chip communication, but since your net output depends on total package performance, the shortened distance between two silicon wafers and increased interconnection outweigh the disadvantages of not having everything on a single SOC. The advantage of this is that you can use "known good chips" -- or smaller silicon wafers -- to piece together larger and more complex packages very quickly. It's best to do everything on a single piece of silicon, but the process makes manufacturing much easier, especially at smaller sizes.
Those little pieces of silicon -- often referred to as "little chips" that you've heard of. You can now get small chips designed to fit small silicon functional blocks together by attaching them to a flat silicon substrate.
Small chips and 2.5D packages will probably last a long time, it's very good quality, and it's probably easier to make than full 3D, and it's a lot cheaper, too. In addition, it scales well and can be reused with new small chips, so that a new chip in the same package format can be made simply by replacing the small chip. One of those improvements is the new Zen3, where the package is similar but some small chips get an upgrade. However, this is in the final version of packaging, namely 3D packaging.
3D packaging
3D packaging is the Holy Grail, the ultimate in packaging. Think of it this way, now we can have a huge skyscraper, customize a huge skyscraper, use any process to fit the function. This is 3D packaging -- all packaging is now done on the silicon chip itself. It is the fastest, most energy efficient way to drive larger and more complex structures that are built specifically for the task and will significantly "extend" Moore's Law. We may not be able to get more feature reductions in the future, but now with 3D packaging, we can still improve our chips to resemble the old Moore's Law.
Interestingly, we have a clear example of the entire semiconductor market going 3D -- memory. Memory's push into 3D structures bodes well for the future. Part of the reason NAND has to be 3D is that they are difficult to scale on smaller geometries. Think of memory as a large 3D skyscraper, with each floor connected by an elevator. These are called "TSVS" or silicon through holes.
This is what the future looks like, we might even have GPU/CPU chips stacked on top of each other, or memory stacked on top of the CPU. This is the final frontier, and we're approaching it fast. Within the next 5 years, you may start to see 3D packaging popping up again and again.
Overview of 2.5D/3D Packaging Solutions
Rather than delve into 3D and 2.5D packaging, I thought it best to just list a few processes in use that you might have heard of before. I want to focus here on the processes done by fabs that drive 3D/2.5D integration forward.
One: CoWoS of Taiwan Semiconductor Manufacturing Co., LTD
This seems to be the workhorse of the 2.5D integration process, pioneered by Xilinx.
This process focuses on placing all logic bare chips on the silicon intermediary layer and then on the packaging substrate. Everything is connected by microbumps or balls. This is a classic 2.5D structure.
Two: Taiwan Semiconductor Manufacturing SoIC
Taiwan Semiconductor's 3D packaging platform is relatively new.
Notice this amazing chart of bump density and bond spacing, SoIC is not even close to flip chips or 2.5D in size, and is almost a front-end process in terms of density and feature size.
This is a good comparison of their technology, but note that SoIC actually has a chip stack similar to 3D stack, rather than a mediation layer 2.5D integration.
Three: Samsung XCube
Not to be outdone, Samsung, which has become a much more important contract manufacturing partner in recent years, has a new 3D packaging solution. Check out their XCube video below.
There's not much information here, but I'd like to stress that the A100 was built on Samsung technology, so this is likely the technology that powers Nvidia's latest chips. Also, out of all the companies, Samsung probably has the most TSV experience due to their 3D memory platform, so it's clear that they know what they're doing.
Four: Intel Foevreos
Last but not least is Intel's Foveros 3D package. We may see more implementation from Intel in its "hybrid CPU" process in future 7nm generations and beyond. They made it very clear that this is their focus going forward.
Interestingly, there really isn't much difference between Samsung, Taiwan Semiconductor, or Intel when it comes to 3D technology.
Winners of the Advanced Packaging Revolution
In the past, annual WFE (Wafer Fab Equipment) estimates excluded package estimates, but starting in 2020, they began to include wafer-level packaging. This is a sign of a change in wind direction, and why the middle end is very interesting from here. Another definition of midend is the back end of the production line (BOEL).